1. Field of the Invention
The solution according to embodiments of the present invention relates to the field of the integrated circuits. More specifically, this solution concerns field-effect transistors.
2. Discussion of the Related Art
Field-effect transistors are usually used in various applications; in particular, power field-effect transistors (such as the power MOSFETs, or simply power MOSs) are suitable for the use in industrial applications (for example, for controlling motors).
For this purpose, power MOSs need to be able to withstand high voltages (for example, up to 50-2.000V) and supply high currents (for example, up to 1-100 A). This result is obtained by suitably controlling various features of the power MOSs; in particular, the main parameters that define each power MOS performance are the breakdown voltage (BV) and the output resistance in ON state (Ron).
The breakdown voltage is the voltage that breaks a drain junction (being reverse biased) of the power MOS—hence the BV needs to be maintained high so that the power MOS can withstand the desired voltage. The output resistance is instead the resistance between a source region and a drain region of the power MOS in its linear operating region—hence the output resistance needs to be maintained low so that the power MOS can supply the desired current (without large power losses and heat dissipations). These features are generally in contrast to each other—since high breakdown voltages require to make the MOS transistor in a thick and low-doped epitaxial layer (to have a larger depletion area of the drain junction), while low output resistances require a thin and highly-doped epitaxial layer.
Various solutions have been suggested in an attempt to attenuate the above-mentioned problem. For example, in the last years so called multi-drain (or superjunction) power MOSs have been proposed, which have a very low output resistance even maintaining a very high breakdown voltage. This result is obtained by extending each body region of the power MOS with a drain column (of the same type of conductivity), so as to form drain channels in the epitaxial layer between each pair of adjacent drain columns. This structure distributes an electric field at the drain junction of the power MOS along the drain columns, so that the field is laterally widened; this remarkably increases the breakdown voltage of the power MOS for the same doping of the epitaxial layer (on the contrary, allowing remarkably increasing the doping of the epitaxial layer, and then reducing the output resistance, for the same breakdown voltage).
However this reduction of the output resistance causes a corresponding increase of a saturation current of the power MOS—defined as a constant current supplied by the power MOS in its saturation region, when a voltage that causes the closure of its channel is reached.
For example, the multi-drain power MOSs can have saturation currents 2-5 times higher than the standard power MOSs have (with values up to some hundreds of Ampere).
This may be a serious drawback in limit operating conditions of the power MOS (for example, caused by malfunctioning in a system wherein it is used). A typical scenario is a short-circuit of a load that is driven by the power MOS. In fact, in this situation, the voltage at the power MOS reaches the supply voltage of the system (for example 100-200V), so that the current that crosses it reaches the value of the saturation current (for example, 50-100 A). The corresponding power that has to be dissipated by the power MOS (i.e. 5-20 kW) may cause its breakdown very quickly (in the order of a few ns).
The solution normally used to solve this problem is to connect a current limiter in series to the power MOS.
The current limiter can be of the passive type—wherein the current is automatically limited, so as to obtain an intrinsically safe behavior. In this case, the current limiter is generally made through a component that acts as a resistor with low resistance in a pre-defined range up to a threshold voltage (so as to limit the power loss in normal operating conditions), and as a current generator beyond the threshold voltage (so as to maintain a constant current). On the contrary, in a current limiter of the active type the current is continuously monitored so as to limit the current when it reaches a danger value (so as to avoid any power loss in normal operating conditions).
For example, the current limiters can be implemented by exploiting a conduction channel delimited by regions of opposite type of conductivity. The current flowing in the conduction channel reverse biases a corresponding PN junction; this limits the width of the conduction channel (thereby increasing its resistance), until the conduction channel is completely closed (with the current that remains constant). For example, U.S. Pat. No. 5,747,841 describes a current limiter based on a MOS transistor with a gate terminal left floating or short-circuited to one of its source terminals; U.S. Pat. No. 6,459,108 instead describes a current limiter made in a chip wherein there are provided two floating regions of opposite type of conductivity that define a lateral channel.
In any case, the known solutions need the addition of a further device to the system wherein the power MOS is used; this increases the area and the complexity of the system. Besides, a possible protection device of the power MOS (used to activate the current limiter when the current reaches the danger value) must have a very quick intervention time (for example, of the order of a few ns) to avoid the breakdown of the power MOS caused by its high saturation current; this increases the cost of the device and hence the cost of the whole system.
In its general terms, the solution according to embodiments of the present invention is based on the idea of making a field-effect transistor with self-limited current.
Particularly, different aspects of the solution according to embodiments of the invention are set out in the independent claims. Advantageous features of the same solution are indicated in the dependent claims.